Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-26 Freescale Semiconductor
Figure 17-13. Unified Channel Block Diagram
Programmable
filter
FSM
IF[0:3]
UCIN
UCOUT
ODIS
EDSELEDPOL
Edge detect
Output flip-flop
FCK
Comparator A
(with zero
Prescaler
UCPRE[0:1]
BSL[0:1]
detection)
Comparator B
Register CADR
ENEN
FORCMB
RWCB RQB
Read note 2
Internal counter clock
Read note 1
Counter bus B, C, or D
Counter bus A
FORCMA
MODE[0:6]
UPDATE
Output disable
control bus
ODISSL[0:1]
EMIOSn
EMIOSn
Internal bus
Unified channel
Counter
bus
select
Internal counter
Register A1
Register A2
Register B1
Register B2
Notes:
1. Counter bus A can be driven by either the STAC bus or channel 23. Refer to EMIOS_MCR[ETB].
2. Goes to the finite state machine of the UC[n-1]. These signals are used for QDEC mode.
FLAG
Register CBDR
Channel 0 drives counter bus B, channel 8 drives counter bus C and channel 16 drives counter bus D.
Counter bus B can be selected as the counter for channels 0-7, counter bus C for channels 8-15,
and counter bus D for channels 16-23. Refer to Figure 1-1 and EMIOS_CCRn[BS].
EMIOS_UCn
EMIOS_Flag_Outn
UCPREN
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