Peripheral Bridge (PBRIDGE A and PBRIDGE B)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 5-13
5.4.2.1 Read Cycles
Read accesses are possible with the PBRIDGE when the requested access size is 32-bits or smaller, and is
not misaligned across a 32-bit boundary. 64-bit data reads (not instruction) are not supported.
5.4.2.2 Write Cycles
Write accesses are possible with the PBRIDGE when the requested access size is 32-bits or smaller.
Misaligned writes that cross a 32-bit boundary are not supported. 64-bit data writes (not instruction) are
not supported.
5.4.2.3 Buffered Write Cycles
Single clock write responses to the system bus are possible with the PBRIDGE when the requested write
access is bufferable. If the requested access does not violate the permissions check, and if both master and
peripheral are enabled for buffering writes, the PBRIDGE internally buffers the write cycle. The write
cycle is terminated early with zero system bus wait states. The access proceeds normally on the slave
interface, but error responses are ignored.
All accesses are initiated and completed in order on the slave interface, regardless of buffering. If the
buffer is full, a following write cycle stalls until it can either be buffered (if bufferable) or can be initiated.
If the buffer has valid entries, a following read cycle stalls until the buffer is emptied and the read cycle
can be completed.
5.4.3 General Operation
Slave peripherals are modules that contain readable/writable control and status registers. The system bus
master reads and writes these registers through the PBRIDGE. The PBRIDGE generates module enables,
the module address, transfer attributes, byte enables, and write data as inputs to the slave peripherals. The
PBRIDGE captures read data from the slave interface and drives it on the system bus.
Separate interface ports are provided for on-platform and off-platform peripherals. The distinction
between on-platform and off-platform is made to allow platform-based designs incorporating the
PBRIDGE to separate the interface ports to allow for ease of timing closure. In addition, module selects
and control register storage for on-platform peripherals are allocated at synthesis time, allowing only
needed resources to be implemented. Off-platform module selects and control register storage do not have
the same degree of configurability.
The modules that are on-platform and those that are off-platform are detailed in Table 5-7.
Table 5-7. On-Platform and Off-Platform Peripherals
On-Platform Off-Platform
Enhanced direct memory access (eDMA) Deserial serial peripheral interface (DSPI)
PBridge A and B Enhanced queued analog-to-digital converter (eQADC)
Interrupt controller (INTC) Enhanced serial communication interface (eSCI)
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