NXP Semiconductors MPC5566 - External Signal Description

MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 22-5
22.2 External Signal Description
22.2.1 Overview
The FlexCAN2 module has two I/O signals connected to the external MCU pins. These signals are
summarized in Table 22-1 and described in more detail in the next sub-sections.
22.2.2 Detailed Signal Description
22.2.2.1 CNRXx
This pin is the receive pin to the CAN bus transceiver. The dominant state is represented by logic level 0.
The recessive state is represented by logic level 1.
22.2.2.2 CNTXx
This pin is the transmit pin to the CAN bus transceiver. The dominant state is represented by logic level 0.
The recessive state is represented by logic level 1.
22.3 Memory Map/Register Definition
This section describes the registers and data structures in the FlexCAN2 module. The addresses presented
are relative to the base address of the module.
The address space occupied by FlexCAN2 is contiguous:
• 128 bytes for registers starting at the module base address
• Extra space for message buffer storage
• 1024 bytes for 64 message buffers
Table 22-1. FlexCAN2 Signals
Signal Name
1
1
x indicates FlexCAN2 module A, B, C, or D.
Direction Description
CNRXx I CAN receive
CNTXx O CAN transmit