NXP Semiconductors MPC5566 - Arbitration and Matching Timing

MPC5566 Microcontroller Reference Manual, Rev. 2
22-32 Freescale Semiconductor
22.4.5.5 Arbitration and Matching Timing
During normal transmission or reception of frames, the arbitration, match, move in and move out processes
are executed during certain time windows inside the CAN frame, as shown in Figure 22-15. When doing
matching and arbitration, FlexCAN2 needs to scan the whole message buffer memory during the available
time slot. To have sufficient time to do that, the following restrictions must be observed:
• A valid CAN bit timing must be programmed, as indicated in Figure 22-15.
• The system clock frequency cannot be smaller than the oscillator clock frequency, i.e. the PLL
cannot be programmed to divide down the oscillator clock.
• There must be a minimum ratio of 16 between the system clock frequency and the CAN bit rate.
Figure 22-15. Arbitration, Match and Move Time Windows
22.4.6 Modes of Operation Details
22.4.6.1 Freeze Mode
This mode is entered by asserting the HALT bit in the CANx_MCR or when the MCU is put into debug
mode. In both cases it is also necessary that the FRZ bit is asserted in the CANx_MCR. When freeze mode
is requested during transmission or reception, FlexCAN2 does the following:
• Waits to be in either intermission, passive error, bus off or idle state
• Waits for all internal activities like move in or move out to finish
• Ignores the RX input pin and drives the TX pin as recessive
• Stops the prescaler, thus halting all CAN protocol activities
• Grants write access to the CANx_ECR, which is read-only in other modes
• Sets the NOTRDY and FRZACK bits in CANx_MCR
After requesting freeze mode, the user must wait for the FRZACK bit to be asserted in CANx_MCR before
executing any other action, otherwise FlexCAN2 can operate in an unpredictable way. In freeze mode, all
memory mapped registers are accessible; CANx_RXIMRn registers can be programmed only if the
MBFEN bit is asserted.
Exit freeze mode using one of the following methods:
• CPU negates the FRZ bit in the CANx_MCR
• The MCU exits debug mode and/or the HALT bit negates.
CRC (15) EOF (7)
Interim
Start move
Matching and arbitration window (24 bits)
Move
(bit 6)
window