Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-25
NOTE
When the FRZ bit in the EMIOS_MCR is set and the module is in debug
mode, the operation of the GCP submodule is not affected; there is no freeze
function in this submodule.
17.4.4 Unified Channel (UC)
Figure 17-13 shows the unified channel block diagram. Each unified channel consists of the following:
• Counter bus select that sets the time base used for all timing functions by the channel
• Programmable clock prescaler
• Two double buffered data registers A and B that allow up to two input capture and/or output
compare events to occur before software intervention is needed.
• Two comparators (equal only) A and B that compare the selected counter bus with the value in the
data registers
• Internal counter for use as a local time base or to count input events
• Programmable input filter that ensures that only valid pin transitions are received by a channel
• Programmable input edge-detector that detects rising, falling, or both edges
• Output flip-flop that holds the logic level applied to the output pin
• eMIOS status and control registers
• Output disable input selector that assigns an output-disabled input signal for use as the unified
channel output disable
• Control state machine (FSM)
The major components and functions of the unified channels are discussed in Section 17.4.4.1,
“Programmable Input Filter (PIF)” through Section 17.4.4.4, “Unified Channel Operating Modes.”
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