NXP Semiconductors MPC5566 - TBDIP Effect on Burst Transfer

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-42 Freescale Semiconductor
12.4.2.5.1 TBDIP Effect on Burst Transfer
Some memories require different timing on the BDIP signal than the default to run burst cycles. Using the
default value of TBDIP = 0 in the appropriate EBI base register results in BDIP being asserted (SCY + 1)
cycles after the address transfer phase, and being held asserted throughout the cycle regardless of the wait
states between beats (BSCY). Figure 12-25 shows an example of the TBDIP = 0 timing for a four-beat
burst with BSCY = 1.
Figure 12-25. Burst 32-bit Read Cycle, One Wait State between Beats, TBDIP = 0
DATA is valid
Wait state
Wait state
CLKOUT
ADDR[8:31]
BDIP
DATA[0:31]
TA
RD_WR
TSIZ[0:1]
TS
OE
CS[n]
Expects more data
ADDR[29:31] = ‘000’
‘00’
Wait state Wait state