NXP Semiconductors MPC5566 - MII Management Frame Register (MMFR)

Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
15-16 Freescale Semiconductor
15.3.4.2.6 MII Management Frame Register (MMFR)
The MMFR is accessed by the application and does not reset to a defined value. The MMFR register is
used to communicate with the attached MII compatible PHY devices, providing read/write access to their
MII registers. Performing a write to the MMFR generates a management frame unless the MSCR is cleared
to 0. If you write to MMFR when MSCR = 0, and then set the MSCR register to a non-zero value, an MII
frame is generated with the data previously written to the MMFR. This allows you to program MMFR and
MSCR in either order if MSCR is currently zero.
Table 15-9 describes the fields and functions for the MII management frame register:
To perform a read or write operation on the MII management interface, the MMFR register must be written
by the application. To generate a valid read or write management frame, the ST field must be written with
a 01 pattern, and the TA field must be written with a 10. If other patterns are written to these fields, a frame
is generated but does not comply with the IEEE® 802.3 MII definition.
To generate an IEEE® 802.3-compliant MII management interface write frame (write to a PHY register),
the application must write {01 01 PHYAD REGAD 10 DATA} to the MMFR register. Writing this pattern
Address: Base + 0x0040 Access: User R/W
0 123456 7 891011121314 15
R
ST OP PA RA TA
W
Reset U
1
UUUUUUUUUUUUU U U
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DATA
W
ResetUUUUUUUUUUUUUU U U
1
“U” signifies a bit that is uninitialized.
Figure 15-8. MII Management Frame Register (MMFR)
Table 15-9. MMFR Field Descriptions
Field Description
0–1
ST
Start of frame delimiter. These bits must be programmed to 01 for a valid MII management frame.
2–3
OP
Operation code. This field must be programmed to 10 (read) or 01 (write) to generate a valid MII
management frame. A value of 11 produces “read” frame operation while a value of 00 produces
“write” frame operation, but these frames are not MII compliant.
4–8
PA
PHY address. This field specifies one of up to 32 attached PHY devices.
9–13
RA
Register address. This field specifies one of up to 32 registers within the specified PHY device.
14–15
TA
Turn around. This field must be programmed to 10 to generate a valid MII management frame.
16–31
DATA
Management frame data. This is the field for data to be written to or read from the PHY register.