NXP Semiconductors MPC5566 - Bus Interface Unit (BIU)

e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
3-32 Freescale Semiconductor
3.3.4 Bus Interface Unit (BIU)
The BIU encompasses control and data signals supporting instruction and data transfers. A data bus width
of 64-bits is implemented. The memory interface supports read and write transfers of 8, 16, 24, 32, and 64
bits, supports burst transfers of four doublewords, and operates in a pipelined fashion.
Single-beat transfers are supported for cache-inhibited read and write cycles, and write-buffer writes. Burst
transfers of four doublewords are supported for cache linefill and copyback operations.
3.3.5 Timer Facilities
The core provides a set of registers to provide fixed interval timing and watchdog functions for the system.
All of these must be initialized during start-up. The registers associated with fixed interval timer and
watchdog functions are the following:
• Timer control register (TCR)—provides control of the timer and watchdog facilities.
• Timer status register (TSR)—provides status of the timer facilities.
• Time base registers (TBU and TBL)—two 32-bit registers (upper and lower) that are concatenated
to provide a long-period, 64-bit counter.
Debug IVOR 15 DE, IDM CSSR[0:1] Debugger when HIDO[DAPUEN] = 0. Caused by trap,
instruction address compare, data address compare,
instruction complete, branch taken, return from interrupt,
interrupt taken, debug counter, external debug event,
unconditional debug event
DE, IDM DSRR[0:1] Debugger when HIDO[DAPUEN] = 1, and caused by same
conditions as above.
Reserved IVOR 16–31
SPE
unavailable
exception
IVOR 32 — SRR[0:1] SPE APU instruction when MSR[SPE] = 0, and see Section
5.6.18 “SPE APU Unavailable Interrupt” in the e200Z6
PowerPC
TM
Core Reference Manual, Rev 0.
SPE data
exception
IVOR 33 — SRR[0:1] SPE FP data exception and see Section 5.6.19 “SPE
Floating-Point Data Interrupt” in the e200Z6 PowerPC
TM
Core
Reference Manual, Rev 0.
SPE round
exception
IVOR 34 — SRR[0:1] Inexact result from floating-point instruction. See Section
5.6.20 “SPE Floating-Point Round Interrupt” in the e200Z6
PowerPC
TM
Core Reference Manual, Rev 0.
1
CE, ME, EE, DE are in the MSR. DIE, FIE, and WIE are in the TCR. “src” signifies the individual enable for each INTC source.
The debug interrupt, IVOR 15, also requires EDM = 0 (EDM and IDM are in the DBCR0 register).
Table 3-11. Interrupts and Conditions (continued)
Interrupt
Type
Interrupt
Vector Offset
Register
Enables
1
Core Register
in Which
State
Information is
Saved
Causing Conditions