Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
15-26 Freescale Semiconductor
15.3.4.2.16 Descriptor Group Upper Address (GAUR)
The GAUR is written by the application. This register contains the upper 32 bits of the 64-bit hash table
used in the address recognition process for receive frames with a multicast address. This register must be
initialized by the application.
15.3.4.2.17 Descriptor Group Lower Address (GALR)
The GALR register is written by the application. This register contains the lower 32 bits of the 64-bit hash
table used in the address recognition process for receive frames with a multicast address. This register must
be initialized by the application.
Table 15-19. IALR Field Descriptions
Field Description
0–31
IADDR2
The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames
with a unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash
index bit 0.
Address: Base + 0x0120 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
GADDR1
W
Reset U
1
UUUUUUUUUUUUUU U
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
GADDR1
W
ResetUUUUUUUUUUUUUUU U
1
“U” signifies a bit that is uninitialized. See the Preface of the book.
Figure 15-20. Descriptor Group Upper Address Register (GAUR)
Table 15-20. GAUR Field Descriptions
Field Description
0–31
GADDR1
The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address recognition
process for receive frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0
of GADDR1 contains hash index bit 32.
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