NXP Semiconductors MPC5566 - Back-To-Back Transfers in External Master Mode

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-67
Figure 12-44. Single-Beat CS Read Cycle in External Master Mode, Zero Wait States
12.4.2.10.4 Back-to-Back Transfers in External Master Mode
The following timing diagrams show examples of back-to-back accesses in external master mode. In these
examples, the reads and writes shown are to a shared external memory, and the EBI is assumed to be
configured for internal arbitration while the external master is configured for external arbitration.
Figure 12-45 shows an external master read followed by an MCU read to the same chip select bank.
Figure 12-46 shows an MCU read followed by an external master read to a different chip select bank.
Figure 12-47 shows an external master read followed by an external master write to a different chip select
bank. This case assumes the MCU has no higher priority internal request pending and is able to park the
external master on the bus.
Receive bus busy negated for second cycle
Assert BB drive address and assert TS
Using the internal arbiter
CLKOUT
BR (Input)
RD_WR
TSIZ[0:1]
BDIP
BG
BB
ADDR[8:31]
DATA[0:31]
TS
TA
CS[n]
OE
DATA is valid