External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-68 Freescale Semiconductor
Figure 12-45. External Master Read followed by MCU Read to Same CS Bank
DATA is valid DATA is valid
External master and MCU off
External master starts read access
Receive bus grant and bus busy negated for second cycle
Using the internal arbiter
External master starts read access
Both masters off
RD_WR
TSIZ[0:1]
BDIP
BB
ADDR[8:31]
DATA[0:31]
TS
TA
CS[n]
OE
CLKOUT
BR (Input)
BG
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