NXP Semiconductors MPC5566 - Features

Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-3
• Combined serial interface (CSI) configuration where the DSPI operates in both SPI and DSI
configurations interleaving DSI frames with SPI frames, giving priority to SPI frames.
For queued operations the SPI queues reside in internal SRAM which is external to the DSPI. Data
transfers between the queues and the DSPI FIFOs are done using the eDMA controller or host software.
Figure 20-2 shows a DSPI with external queues in internal SRAM.
Figure 20-2. DSPI with Queues and eDMA
20.1.3 Features
The DSPI supports these SPI features:
• Full-duplex, three-wire synchronous transfers
• Master and slave mode
• Buffered transmit and receive operation using the TX and RX FIFOs, with depths of four entries
• Visibility into TX and RX FIFOs for ease of debugging
• FIFO bypass mode for low-latency updates to SPI queues
• Programmable transfer attributes on a per-frame basis
— Eight clock and transfer attribute registers
— Serial clock with programmable polarity and phase
— Programmable delays
– PCS to SCK delay
– SCK to PCS delay
– Delay between frames
— Programmable serial frame size of 4 to 16 bits, expandable with software control
— Continuously held chip select capability
• Six peripheral chip selects, expandable to 64 with external demultiplexer
• Deglitching support for up to 32 peripheral chip selects with external demultiplexer
Internal SRAM
TX queue
RX queue
Address/control
TX FIFO
DSPI
RX FIFO
RX data
TX data
TX data RX data
Shift register
eDMA controller
Address/control
or host CPU