Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 18-33
18.4.5 Global Channel Registers
The registers in this section group, by type, the interrupt status and enable bits from all the channels. This
organization eases management of all channels or groups of channels by a single interrupt handler routine.
These bits are mirrored by the individual channel registers.
18.4.5.1 eTPU Channel Interrupt Status Register (ETPU_CISR)
Host interrupt status from all channels are grouped in ETPU_CISR. The bits are mirrored by the channels’
status/control registers. For more information, refer to Section 18.4.6.3, “eTPU Channel n Status Control
Register (ETPU_CnSCR),” and the eTPU Reference Manual.
NOTE
The host core must write 1 to clear (w1c) an interrupt status bit.
17
RSC2
TCR2
2
resource server/client assignment. Selects the eTPU data resource assignment to be used as a server or
client. RSC2 selects the functionality of TCR2. For server mode, external plugging determines the unique server
address assigned to each TCR. For a client mode, the SRV2 field determines the Server address to which the client
listens.
0 Resource Client operation.
1 Resource Server operation.
18–19 Reserved
20–23
SERVER
_ID2
STAC bus address for TCR2 as a server.
24–27 Reserved
28–31
SRV2
[0:3]
TCR2 resource server. Selects the address of the specific STAC server the local TCR2 listens to when configured
as a STAC Client. For more information on the STAC interface, refer to the eTPU Reference Manual.
1
Resource identifies any parameter that changes in time and can be exported / imported from other device. For the eTPU, a
resource can be TCR1 or TCR2 (either time or angle values).
2
When TCR2 is configured as a STAC bus client (REN2 = 1, RSC2 = 0) the angle clock hardware must be disabled
(ETPU_TBCR[AM] = 0).
Table 18-14. ETPU_REDCR Field Descriptions (continued)
Field Description
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