External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-2 Freescale Semiconductor
The following figure shows the MPC5566 EBI block diagram on the 416 package. The BR, BG, and BB
signals are used for arbitration on the external bus:
Figure 12-1. EBI Block Diagram
12.1.2 Overview
The EBI includes a memory controller that generates interface signals to support a variety of external
memories. This includes single data rate (SDR) burst mode flash, external SRAM, and asynchronous
memories. It supports up to four regions (via chip selects), each with its own programmed attributes.
External Bus
Interface
Memory
controller
External master
controller
Bus
monitor
Registers
Arbiter
Slave
interface/
CLKOUT driver
CLKOUT
crossbar switch
(XBAR)
Master
interface/
crossbar switch
(XBAR)
Peripheral
bridge
ADDR[6:31]
DATA[0:31]
CS[0:3]
TS
WE/BE[0:3]
OE
TSIZ[0:1]
RD_WR
BDIP
TA
TEA
BR
BG
BB
CAL_DATA[0:15]
(PBridge A)
system bus
system bus
Available on the
496 VertiCal assembly only.
CAL_ADDR[12:30]
CAL_WE/BE[0:1]
CAL_TS
CAL_OE
CAL_RD_WR
CAL_CS[0:3]
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