Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
15-14 Freescale Semiconductor
Table 15-6 describes the receive descriptor active register (RDAR):
15.3.4.2.4 Transmit Descriptor Active Register (TDAR)
The TDAR is a command register that must be written by the application to indicate that the transmit
descriptor ring has been updated (transmit buffers have been produced by the driver with the ready bit set
in the buffer descriptor).
Whenever the register is written, the X_DES_ACTIVE bit is set. This value is independent of the data
actually written by the application. When set, the FEC polls the transmit descriptor ring and processes
transmit frames (provided ECR[ETHER_EN] is also set). Once the FEC polls a transmit descriptor and
the ready bit is not set, the FEC clears X_DES_ACTIVE and stops polling the transmit descriptor ring until
you set the bit again, signifying additional descriptors were placed in the transmit descriptor ring.
The TDAR register is cleared at reset, when ECR[ETHER_EN] is cleared, or when ECR[RESET] is set.
Address: Base + 0x0010 Access: User R/W
0 123456 7 89101112131415
R0 000000
R_DES_
ACTIVE
00000000
W
Reset0000000 0 00000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0000000 0 00 000000
W
Reset0000000 0 00000000
Figure 15-5. Receive Descriptor Active Register (RDAR)
Table 15-6. RDAR Field Descriptions
Field Description
0–6 Reserved, must be cleared.
7
R_DES_ACTIVE
Set to one when this register is written, regardless of the value written. Cleared by the FEC device
whenever no additional “empty” descriptors remain in the receive ring. Also cleared when
ECR[ETHER_EN] is cleared.
8–31 Reserved, must be cleared.
Address: Base + 0x0014 Access: User R/W
0 123456 7 89101112131415
R0 000000
X_DES_
ACTIVE
00000000
W
Reset0000000 0 00000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0000000 0 00 000000
W
Reset0000000 0 00000000
Figure 15-6. Transmit Descriptor Active Register (TDAR)
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