NXP Semiconductors MPC5566 - DSPI POP RX FIFO Register (Dspix_Popr)

Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-25
20.3.2.7 DSPI POP RX FIFO Register (DSPIx_POPR)
The DSPIx_POPR allows you to read the RX FIFO. See Section 20.4.3.5, “Using the RX FIFO Buffering
Mechanism” for a description of the RX FIFO operations. Eight or 16-bit read accesses to the
DSPIx_POPR fetch the RX FIFO data, and update the counter and pointer.
NOTE
Reading the RX FIFO field fetches data from the RX FIFO. Once the RX
FIFO is read, the read data pointer is moved to the next entry in the RX
FIFO. Therefore, read DSPIx_POPR only when you need the data. For
compatibility, configure the TLB (MMU table) entry for DSPIx_POPR as
guarded.
10–15
PCSx
Peripheral chip select x. Selects which PCSx signals are asserted for the transfer.
0 Negate the PCSx signal
1 Assert the PCSx signal
Note: Use in SPI master mode only.
16–31
TXDATA
[0:15]
Transmit data. Holds SPI data for transfer according to the associated SPI command.
Note: Use TXDATA in master and slave modes.
Address: Base + 0x0038 Access: R/O
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RRXDATA
W
Reset0000000000000000
Figure 20-9. DSPI POP RX FIFO Register (DSPIx_POPR)
Table 20-8. DSPIx_PUSHR Field Descriptions (continued)
Field Description