NXP Semiconductors MPC5566 - Etpu Channel Data Transfer Request Status Register (ETPU_CDTRSR)

Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
18-34 Freescale Semiconductor
18.4.5.2 eTPU Channel Data Transfer Request Status Register (ETPU_CDTRSR)
Data transfer request status from all channels are grouped in ETPU_CDTRSR. The bits are mirrored by
the channels’ status/control registers. For more information on data transfers and channel control registers,
refer to the eTPU Reference Manual.
In the MPC5566, eTPU A channels [0:2,12:15,28:29] and eTPU B channels
[0:3,12:15,28:31] are connected to the DMA. The data transfer request lines
that are not connected to the DMA controller are not connected and do not
generate transfer requests, even if their request status bits are asserted in
registers ETPU_CDTRSR and ETPU_CnSCR. Channels that are not
connected can still have their status bits (DTRSn) cleared by writing a 1 to
the appropriate field.
Address: Base + 0x0000_0200 (eTPU A)
Address: Base + 0x0000_0204 (eTPU B)
Access: R/W1c
0123456789101112131415
R CIS31 CIS30 CIS29 CIS28 CIS27 CIS26 CIS25 CIS24 CIS23 CIS22 CIS21 CIS20 CIS19 CIS18 CIS17 CIS16
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CIS15 CIS14 CIS13 CIS12 CIS11 CIS10 CIS9 CIS8 CIS7 CIS6 CIS5 CIS4 CIS3 CIS2 CIS1 CIS0
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset0000000000000000
Figure 18-14. eTPU Channel Interrupt Status Register (ETPU_CISR)
Table 18-15. ETPU_CISR Field Descriptions
Field Description
0–31
CISn
Channel n interrupt status.
0 indicates that channel n has no pending interrupt to the host core.
1 indicates that channel n has a pending interrupt to the host core.
To clear a status bit, the host must write 1 to it.
For details about interrupts refer to the eTPU Reference Manual.