NXP Semiconductors MPC5566 - ADC Time Base Counter Registers (ADC_TBCR)

Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-40 Freescale Semiconductor
NOTE
If TBC_CLK_PS is not set to disabled, it must not be changed to any other
value besides disabled. If TBC_CLK_PS is set to disabled it can be changed
to any other value.
19.3.3.3 ADC Time Base Counter Registers (ADC_TBCR)
The ADC_TBCR contains the current value of the time base counter. ADC_TBCR can be accessed by
configuration commands sent to ADC0 or to ADC1. A data write to ADC_TBCR using a configuration
command sent to ADC0 writes the same memory location as a write using a configuration command sent
to ADC1.
Table 19-29. ADC_TSCR Field Descriptions
Field Description
0–11 Reserved.
12–15
TBC_
CLK_PS
[0:3]
Time base counter clock prescaler. Contains the system clock divide factor for the time base counter. It controls the
accuracy of the time stamp. The prescaler is disabled when TBC_CLK_PS is set to 0b0000.
Table 19-30. Clock Divide Factor for Time Stamp
TBC_CLK_PS[0:3]
System Clock Divide
Factor
Clock to Time Stamp
Counter for a 120 MHz
System Clock (MHz)
0b0000 Disabled Disabled
0b0001 1 120
0b0010 2 60
0b0011 4 30
0b0100 6 20
0b0101 8 15
0b0110 10 12
0b0111 12 10
0b1000 16 7.5
0b1001 32 3.75
0b1010 64 1.88
0b1011 128 0.94
0b1100 256 0.47
0b1101 512 0.23
0b1110–0b1111 Reserved —