Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5566 Microcontroller Reference Manual, Rev. 2
11-20 Freescale Semiconductor
11.4.1.2 Software Controlled Power Management/Clock Gating
Some of the IP modules on this device support software controlled power management/clock gating
whereby the application software can disable the non-memory-mapped portions of the modules by writing
to module disable (MDIS) bits in registers within the modules. The memory-mapped portions of the
modules are clocked by the system clock when they are being accessed. The NPC can be configured to
disable the MCKO signal when there are no Nexus messages pending. The H7FA flash array can be
disabled by writing to a bit in the Flash register map.
The modules that implemented software controlled power management and clock gating are listed in
Table 11-6 along with the registers and bits that disable each module. The software controlled clocks are
enabled when the MCU comes out of reset.
11.4.1.3 Clock Dividers
Each of the CLKOUT, MCKO, and ENGCLK dividers provides a nominal 50% duty cycle clock to an
output pin. There is no guaranteed phase relationship between CLKOUT, MCKO, and ENGCLK.
ENGCLK is not synchronized to any I/O pins.
Table 11-6. Software Controlled Power Management/Clock Gating Support
Module Name Register Name Bit Names
DSPI A DSPI_A_MCR MDIS
DSPI B DSPI_B_MCR MDIS
DSPI C DSPI_C_MCR MDIS
DSPI D DSPI_D_MCR MDIS
EBI EBI_MCR MDIS
eTPU engine A ETPU_ECR_1 MDIS
eTPU engine B ETPU_ECR_2 MDIS
FlexCAN A CAN_A_MCR MDIS
FlexCAN B CAN_B_MCR MDIS
FlexCAN C CAN_C_MCR MDIS
FlexCAN D CAN_D_MCR MDIS
eMIOS EMIOS_MCR MDIS
eSCI A ESCI_A_CR2 MDIS
eSCI B ESCI_B_CR2 MDIS
Nexus port controller (NPC) NPC_PCR MCKO_EN, MCKO_GT
1
1
Refer to Chapter 25, “Nexus Development Interface.”
Flash array FLASH_MCR STOP
2
2
Refer to Chapter 13, “Flash Memory.”
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