NXP Semiconductors MPC5566 - External Clock Control Register (SIU_ECCR)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-116 Freescale Semiconductor
6.3.1.165 External Clock Control Register (SIU_ECCR)
The SIU_ECCR controls the timing relationship between the system clock and the external clocks
ENGCLK and CLKOUT. All bits and fields in the SIU_ECCR are read/write and are reset by the
synchronous reset signal.
30 CSRE The CRSE bit enables the suppression of reflection from the EBI’s calibration bus onto
the non-calibration bus. The EBI drives some outputs to both the calibration and
non-calibration busses. When CRSE is asserted, the values driven onto the calibration
bus are not reflected onto the non-calibration bus pins. When CRSE is negated, the
values driven onto the calibration bus are reflected onto the non-calibration bus. CRSE
only enables reflection suppression for the non-calibration bus pins that do not have a
negated state to which the pins return at the end of the access. CRSE does not enable
reflection suppression for the non-calibration bus pins that have a negated state to
which the pins return at the end of an access. Those reflections always are
suppressed. Furthermore, the suppression of reflections from the non-calibration bus
onto the calibration bus is not enabled by CRSE. Those reflections also always are
suppressed.
0 Calibration reflection suppression is enabled.
1 Calibration reflection suppression is disabled.
31 TEST
Test mode enable. Allows reads or writes to undocumented registers used only for
production tests. Since these production test registers are undocumented, estimating
the impact of errant accesses to them is impossible. Do not change this bit from its
negated state at reset.
0 Undocumented production test registers cannot be read or written.
1 Undocumented production test registers can be read or written.
Address: Base + 0x0984 Access: R/W
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0
ENGDIV
0000
EBTS
0
EBDF
W
Reset0000000000000001
Figure 6-165. External Clock Control Register (SIU_ECCR)
Table 6-153. SIU_CCR Field Descriptions
Bits Name Description