Enhanced Serial Communication Interface (eSCI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 21-23
When the transmit shift register is not transmitting a frame, the TXD output goes to the idle condition,
logic 1. If at any time software clears the TE bit in eSCI control register 1 (ESCIx_CR1), the transmit
enable signal goes low and the TXD output goes idle.
If software clears TE while a transmission is in progress (ESCIx_CR1[TC] = 0), the frame in the transmit
shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always
wait for TDRE to go high after the last frame before clearing TE.
To separate messages with preambles with minimum idle line time, use the following sequence between
messages:
1. Write the last byte of the first message to ESCIx_DR.
2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift
register.
3. Queue a preamble by clearing and then setting the TE bit.
4. Write the first byte of the second message to ESCIx_DR.
21.4.4.3 Break Characters
Setting the break bit, SBK, in eSCI control register 1 (ESCIx_CR1) loads the transmit shift register with a
break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character
length depends on the M bit in the eSCI control register 1 (ESCIx_CR1) and on the BRK13 bit in the eSCI
control register 2 (ESCIx_CR2). As long as SBK is set, the transmitter logic continuously loads break
characters into the transmit shift register. After software clears the SBK bit, the shift register finishes
transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the
end of a break character guarantees the recognition of the start bit of the next frame.
NOTE
LIN 2.0 requires that a break character be 13-bits long, so always set the
BRK13 bit to 1. The eSCI works with BRK13 = 0, but it violates LIN 2.0.
The eSCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a
logic 0 where the stop bit should be. Receiving a break character has the following effects on eSCI
registers:
• Sets the framing error flag, FE.
• Sets the receive data register full flag, RDRF.
• Clears the eSCI data register (ESCIx_DR).
• Can set a flag: overrun (OR), noise flag (NF), parity error flag (PF), or the receiver active flag
(RAF). For more details, refer to Section 21.3.3.4, “eSCI Status Register (ESCIx_SR).”
21.4.4.4 Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on
the M bit in eSCI control register 1 (ESCIx_CR1). The preamble is a synchronizing idle character that
begins the first transmission initiated after toggling the TE bit from 0 to 1.
To Next Page
Loading...
