NXP Semiconductors MPC5566 - System Configuration Registers

Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
18-18 Freescale Semiconductor
18.4.3 System Configuration Registers
18.4.3.1 eTPU Module Configuration Register (ETPU_MCR)
This register is global to both eTPU engines, and resides in the shared BIU. ETPU_MCR gathers global
configuration and status in the eTPU system, including global exception. It is also used for configuring the
SCM (shared code memory) operation and test.
Base + (0x0001_0000–0x0001_4FFF) SCM Shared Code Memory
3
20 KB
Base + (0x0001_5000–0x0001_FFFF) — Reserved —
1
The register at this address is available only on the MPC5554 and the MPC5566.
2
Parameter sign extension access area. Refer to the eTPU Reference Manual.
3
SCM access is only available under certain conditions when ETPU_MCR[VIS] = 1. The SCM can only be written in 32-bit
accesses.
Address: Base + 0x0000_0000 Access: R/W
0123 4 5 6789101112131415
R0000MGEAMGEBILFAILFB000 SCMSIZE
WGEC
Reset0000 0 0 00000 SCMSIZE
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0000 0
SCMM
ISF
SCM
MISEN
00
VIS
00000
GTBE
W
Reset0000 0 0 0000000000
Figure 18-5. eTPU Module Configuration Register (ETPU_MCR)
Table 18-6. ETPU_MCR Field Descriptions
Field Description
0
GEC
Global exception clear. Negates global exception request and clears global exception status bits MGEA, MGEB,
ILFA, ILFB and SCMMISF. A read always returns 0. Writes have the following effect:
0 Keep global exception request and status bits ILFA, ILFB, MGEA, MGEB, and SCMMISF as is.
1 Negate global exception, clear status bits ILFA, ILFB, MGEA, MGEB, and SCMMISF.
GEC works the same way with either one or both engines in stop mode.
1–3 Reserved
Table 18-5. Detailed Memory Map (continued)
Address Register Name Register Description Bits