NXP Semiconductors MPC5566 - CFIFO Prioritization and Command Transfer

Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-62 Freescale Semiconductor
Figure 19-36. CFIFO Entry Pointer Example
19.4.3.2 CFIFO Prioritization and Command Transfer
The CFIFO priority is fixed according to the CFIFO number. A CFIFO with a smaller number has a higher
priority. When commands from different CFIFOs are sent to the same destination (such as the same
on-chip ADC), the higher priority CFIFO is always served first. A triggered, not-underflowing CFIFO
starts to transfer commands when the following occur:
• Its commands are bound for an internal command buffer that is not full, and it is the highest priority
triggered CFIFO sending commands to that buffer.
First In
Transfer
Next
Data
Pointer
Last In
Push
Next
Data
Pointer
CFIFOn
Transfer
Next
Data
Pointer
Push
Next
Data
Pointer
CFIFOn
First In
Transfer
Next
Data
Pointer
Last In
Push
Next
Data
Pointer
CFIFOn
After Reset or
Invalidation
Some Entries Pushed
but None Executed
No Entries Pushed
but Some Executed
First In
Transfer
Next
Data
Pointer
Push
Next
Data
Pointer
CFIFOn
Transfer
Next
Data
Pointer
Push
Next
Data
Pointer
CFIFOn
First In
Transfer
Next
Data
Pointer
Last In
Push
Next
Data
Pointer
CFIFOn
No Entries Pushed
but Some Executed
Some Entries Pushed
and Some Executed
Entries Pushed Until
Full and None Executed
First In
Last In Last In
Valid Entry
Empty Entry
NOTE:
n = 0, 1, 2, 3, 4, 5