NXP Semiconductors MPC5566 - Configuring the NDI for Nexus Messaging

Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 25-11
25.4.2 Configuring the NDI for Nexus Messaging
The NDI is placed in disabled mode upon exit of power-on reset. If message transmission via the auxiliary
port is desired, a write to the port configuration register (PCR) located in the NPC is then required to enable
the NDI and select the mode of operation. Asserting MCKO_EN in the PCR places the NDI in enabled
mode and enables MCKO. The frequency of MCKO is selected by writing the MCKO_DIV field.
Asserting or negating the FPM bit selects full-port or reduced-port mode, respectively. When writing to
the PCR, the PCR lsb (least significant bit) must be written to a logic 0. Setting the lsb of the PCR enables
factory debug mode and prevents the transmission of Nexus messages.
Table 25-6 describes the NDI configuration options.
Table 25-4. JTAG Client Select Instructions
JTAGC Instruction Opcode Description
ACCESS_AUX_TAP_NPC 10000 Enables access to the NPC TAP controller
ACCESS_AUX_TAP_ONCE 10001 Enables access to the e200z6 OnCE TAP controller
ACCESS_AUX_TAP_eTPU 10010 Enables access to the eTPU Nexus TAP controller
ACCESS_AUX_TAP_DMA 10011 Enables access to the eDMA Nexus TAP controller
Table 25-5. Nexus Client JTAG Instructions
Instruction Description Opcode
NPC JTAG Instruction Opcodes
NEXUS_ENABLE Opcode for NPC Nexus Enable instruction (4-bits) 0x0
BYPASS Opcode for the NPC BYPASS instruction (4-bits) 0xF
e200z6 OnCE JTAG Instruction Opcodes
1
1
Refer to the e200z6 Reference Manual for a complete list of available OnCE instructions.
NEXUS3_ACCESS Opcode for e200z6 OnCE Nexus Enable instruction (10-bits) 0x7C
BYPASS Opcode for the e200z6 OnCE BYPASS instruction (10-bits) 0x7F
eDMA Nexus JTAG Instruction Opcodes
NEXUS_ACCESS Opcode for eDMA Nexus Enable instruction (4-bits) 0x0
BYPASS Opcode for the eDMA Nexus BYPASS instruction (4-bits) 0xF
Table 25-6. NDI Configuration Options
JCOMP
Asserted
MCKO_EN bit of the Port
Configuration Register
FPM bit of the Port
Configuration Register
Configuration
No X X Reset
Ye s 0 X D i s a b l e d
Yes 1 1 Full-port mode
Yes 1 0 Reduced-port mode