NXP Semiconductors MPC5566 - Non-Chip-Select Burst in 16-Bit Data Bus Mode

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-70 Freescale Semiconductor
Figure 12-47. External Master Read followed by External Master
Write to Different CS
Bank
12.4.2.11 Non-Chip-Select Burst in 16-bit Data Bus Mode
The timing diagrams in this section apply only to the special case of a non-chip select 32-bit access in
16-bit data bus mode. They specify the behavior for both the EBI-master and EBI-slave, as the external
master is expected to be another MCU with this EBI.
For this case, a special two-beat burst protocol is used for reads and writes, so that the EBI-slave can
internally generate one 32-bit read or write access (thus 32-bit coherent), as opposed to two separate 16-bit
accesses.
External master
starts read access
External master
starts read access
Receive bus grant and bus busy
negated for second cycle
Both masters off
DATA is valid
DATA is valid
CLKOUT
BR (Input)
RD_WR
TSIZ[0:1]
BDIP
BG
BB
ADDR[8:31]
DATA[0:31]
TS
TA
CS[n]
OE
CS[y]
WE
Bus grant still
asserted, can do
another access