External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-69
Figure 12-46. MCU Read followed by External Master Read to Different CS Bank
MCU starts read access
Receive bus busy
negated for second cycle
External master and MCU off
Using the internal arbiter
External master starts read access
DATA is valid
Both masters off
RD_WR
TSIZ[0:1]
BDIP
BB
ADDR[8:31]
DATA[0:31]
TS
TA
CS[y]
OE
CLKOUT
BR (Input)
BG
DATA is valid
CS[n]
To Next Page
Loading...
