NXP Semiconductors MPC5566 - Application Initialization (Prior to Asserting ECR[ETHER_EN])

Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
15-32 Freescale Semiconductor
Other registers reset when the ECR[ETHER_EN] bit is cleared. ECR[ETHER_EN] is deasserted by a hard
reset or can be deasserted by software to halt operation. By deasserting ECR[ETHER_EN], the
configuration control registers such as the TCR and RCR are not reset, but the entire data path is reset.
15.4.2 Application Initialization (Prior to Asserting ECR[ETHER_EN])
The application must initialize portions of the FEC prior to setting the ECR[ETHER_EN] bit. The exact
values depend on the application. The sequence is not important.
Ethernet MAC registers requiring initialization are defined in Table 15-29.
FEC FIFO/DMA registers that require initialization are defined in Table 15-30.
Table 15-28. ECR[ETHER_EN] De-Assertion Effect on FEC
Register/Machine Reset Value
XMIT block Transmission is aborted (bad CRC
appended)
RECV block Receive activity is aborted
DMA block All DMA activity is terminated
RDAR Cleared
TDAR Cleared
Descriptor Controller block Halt operation
Table 15-29. Application Initialization (Before ECR[ETHER_EN])
Description
Initialize EIMR
Clear EIR (write 0xFFFF_FFFF)
TFWR (optional)
IALR and IAUR
GAUR and GALR
PALR and PAUR (only needed for full duplex flow control)
OPD (only needed for full duplex flow control)
RCR
TCR
MSCR (optional)
Clear MIB_RAM (locations Base + 0x0200–0x02FC)
Table 15-30. FEC Application Initialization (Before ECR[ETHER_EN])
Description
Initialize FRSR (optional)
Initialize EMRBR
Initialize ERDSR