NXP Semiconductors MPC5566 - Detailed Signal Descriptions

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-7
12.2.1 Detailed Signal Descriptions
See Chapter 2, “Signal Description,” as not all signals are implemented in all device packages.
12.2.1.1 Address Lines: ADDR[8:31] or ADDR[6:29]
The ADDR[8:31] or ADDR[6:29] signals specify the physical address of the bus transaction. See
Table 12-1 for details on address bus configuration. The 24 address lines are bits 8 through 31 of the EBI
32-bit internal address bus. Bits 0 through 7 are internally driven by the EBI for externally initiated
accesses depending on the internal slave accessed.
See Section 12.4.2.10.1, “Address Decoding for External Master Accesses,” for more details.
ADDR[8:31] is driven by the EBI or an external master depending on the module that controls the external
bus. During a calibration bus access, ADDR[n] reflects the same values as the CAL_ADDR[n] signals.
12.2.1.2 Data Lines: DATA[0:31]
In the 416 BGA package and 496 assembly, DATA[0:31] signals transfer the data for the current
transaction.
DATA[0:31] is driven by the EBI when it owns the external bus and it initiates a write transaction to an
external device. The EBI also drives DATA[0:31] when an external master owns the external bus and
initiates a read transaction to an internal module.
DATA[0:31] is driven by an external device during a read transaction from the EBI. An external master
drives DATA[0:31] when it owns the bus and initiates a write transaction to an internal module or shared
external memory.
For 8-bit and 16-bit transactions, the unused byte lanes do not supply valid data.
During a calibration bus access, the DATA bus is not driven by the EBI.
BG I/O Bus grant Up 416 496
BR I/O Bus request Up 416 496
1
This column shows which signals require a weak pullup or pulldown. The EBI module does not configure the pullup or
pulldown mechanisms; use the pad configuration registers (PCRs) in the System Integration Unit (SIU_PCRs) to configure
the signal direction and strength requirements.
2
All EBI and calibration signals designed for this device are available on the 496 VertiCal assembly.
3
ADDR[6:7] are separate signals from EBI block, but are muxed onto ADDR[30:31] pins on MCU.
4
CAL_ADDR[10:11] are separate signals from the EBI block, and are muxed onto CAL_CS[2:3] pins on MCU.
5
The CLKOUT signal is driven by the FMPLL Module.
Table 12-3. MPC5566 Signal Properties (continued)
Signal Name I/O Type Function Pull
1
416
Package
496
2
Assembly