NXP Semiconductors MPC5566 - Master Privilege Control Register (Pbridge_X_Mpcr)

Peripheral Bridge (PBRIDGE A and PBRIDGE B)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 5-5
PBRIDGE_B address spaces. The protection and access fields of the MPCR, PACR, and OPACR registers
are 4-bits wide. Although these registers are read/write, the reserved fields shown do not apply to this
device and must remain at the reset value, therefore only write the fields’ reset value to the reserved fields
of these registers.
5.3.1.1 Master Privilege Control Register (PBRIDGE_x_MPCR)
Each master privilege control register (PBRIDGE_x_MPCR) specifies 4-bit access fields defining the
access privilege level associated with a bus master in the platform, as well as specifying whether write
accesses from this master are bufferable. The registers provide one field per bus master. The following
table describes the fields in the PBRIDGE X master privilege control register:
The following table describes the fields in the PBRIDGE master privilege control register:
Address: Base + 0x0000 Access: R/W
0 1 2 3 4 5 6 7 8 9 101112131415
R
MBW0 MTR0 MTW0 MPL0 MBW1 MTR1 MTW1 MPL1 MBW2 MTR2 MTW2 MPL2 MBW3 MTR3 MTW3 MPL3
W
Reset0111011101110111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MBW4 MTR4 MTW4 MPL4
011101110111
W
Reset0111011101110111
Figure 5-2. Master Privilege Control Registers (PBRIDGE_x_MPCR)
Table 5-4. PBRIDGE_x_MPCR Field Descriptions
Field Description
0
MBW0
Master buffer writes. Determines whether the PBRIDGE is enabled to buffer writes from the CPU. Buffered
writes are disabled by default.
0 Buffered write accesses from the CPU are disabled
1 Buffered write accesses from the CPU are enabled
1
MTR0
Master trusted for reads. Determines whether the CPU is trusted for read accesses. Trusted by default.
0 Read accesses from the CPU are not trusted
1 Read accesses from the CPU are trusted
2
MTW0
Master trusted for writes. Determines whether the master is trusted for write accesses. Trusted by default.
0 Write accesses from the CPU are not trusted
1 Write accesses from the CPU are trusted
Access Field 0
Access Field 1
Access Field 2
Access Field 3
Access Field 4
Access Field 5
Access Field 6
Access Field 7