Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 11-19
11.4 Functional Description
This section explains clock architecture, clock operation, and clock configuration.
11.4.1 Clock Architecture
This section describes the clocks and clock architecture in the MCU.
11.4.1.1 Overview
The system clocks are generated from one of four FMPLL modes: crystal reference mode, external
reference mode, dual-controller (1:1) mode, and bypass mode. Refer to Section 11.1, “Introduction” for
information on the different clocking modes available in the FMPLL.
The peripheral IP modules have been designed to allow software to gate the clocks to the
non-memory-mapped logic of the modules.
The MCU has three clock output pins that are driven by programmable clock dividers. The clock dividers
divide the system clock down by even integer values. The three clock output pins are the following:
• CLKOUT – External address/data bus clock
• MCKO – Nexus auxiliary port clock
• ENGCLK – Engineering clock
The MCU has been designed so that the oscillator clock can be selected as the clock source for the CAN
interface in the FlexCAN blocks resulting in very low jitter performance.
Figure 11-1 shows a block diagram of the FMPLL and the system clock architecture.
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CALDONE
Calibration complete. Indicates whether the calibration sequence has been completed since the last time
modulation was enabled. If CALDONE = 0 then the calibration sequence is either in progress or modulation
is disabled. If CALDONE = 1 then the calibration sequence has been completed, and frequency modulation
is operating.
0 Calibration not complete.
1 Calibration complete.
Note: FM relocking does not start until calibration is complete.
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CALPASS
Calibration passed. Indicates whether the calibration routine was successful. If CALPASS = 1 and
CALDONE = 1 then the routine was successful. If CALPASS = 0 and CALDONE = 1, then the routine was
unsuccessful. When the calibration routine is initiated the CALPASS is asserted. CALPASS remains asserted
until either modulation is disabled by clearing the DEPTH bits in the FMPLL_SYNCR or a failure occurs within
the FMPLL calibration sequence.
0 Calibration unsuccessful.
1 Calibration successful.
If calibration is unsuccessful, then actual depth is not guaranteed to match the desired depth.
Table 11-5. FMPLL_SYNSR Field Descriptions (continued)
Field Description
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