MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 22-3
The CAN protocol interface (CPI) manages the serial communication on the CAN bus, requesting RAM
access for receiving and transmitting message frames, validating received messages and performing error
handling. The message buffer management (MBM) handles message buffer selection for reception and
transmission, taking care of arbitration and ID matching algorithms. The bus interface unit (BIU) controls
the access to and from the internal interface bus, to establish connection to the CPU and to any other
modules. Clocks, address and data buses, interrupt outputs and test signals are accessed through the bus
interface unit.
22.1.3 Features
The FlexCAN2 module includes these distinctive features:
• Based on and includes all existing features of the Freescale TouCAN module
• Reception queue available by setting more than one RX message buffer with the same ID
• Programmable for global (compatible with previous versions) or individual receive ID masking
• Maskable self-reception by setting MCR[SRXDIS]
• Full implementation of the CAN protocol specification, version 2.0B
— Standard data and remote frames
— Extended data and remote frames
— Data length of 0–8 bytes
— Programmable bit rate up to 1 Mb/sec
• Content-related addressing
• 64 flexible message buffers of 0–8 bytes data length
• Each MB configurable as RX or TX, all supporting standard and extended messages
• Includes 1024 bytes of RAM used for message buffer storage
• Programmable clock source to the CAN protocol interface, either system clock or oscillator clock
• Listen-only mode capability
• Programmable loop-back mode supporting self-test operation
• Three programmable mask registers are turned off by default:
— Global
— RX Buffer 14
• RX Buffer 15Programmable transmit-first scheme: lowest ID or lowest buffer number
• Time stamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
• Maskable interrupts
• Independent of the transmission medium (an external transceiver is assumed)
• Multi master concept
• High immunity to EMI
• Short latency time due to an arbitration scheme for high-priority messages
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