NXP Semiconductors MPC5566 - Transfer Size 0 through 1 (TSIZ[0:1])

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-11
12.2.1.15 Transfer Size 0 through 1 (TSIZ[0:1])
TSIZ[0:1] indicates the size of the requested data transfer. TSIZ[0:1] is driven by the EBI or an external
master depending on which component controls the external bus. The TSIZ[0:1] signals can be used with
ADDR[30:31] to determine which byte lanes of the data bus are involved in the transfer. For non-burst
transfers, the TSIZ[0:1] signals specify the number of bytes starting from the byte location addressed by
ADDR[30:31]. In burst transfers, the value of TSIZ[0:1] is always 00.
If the SIZEN bit in the EBI_MCR is 1, then TSIZ[0:1] is ignored by the EBI as an input for external master
transactions and the size is instead determined by the SIZE field in the EBI_MCR. The SIZEN bit has no
effect on the EBI when it is mastering a transaction on the external bus. TSIZ[0:1] is still driven by the EBI
and is used by the external master depending on the SIZEN setting for the external master’s EBI. See
Section 12.3.1.3, “EBI Module Configuration Register (EBI_MCR).”
12.2.1.16 Calibration Chip Selects (CAL_CS[0:3])
CAL_CS[n] is asserted by the master to indicate that this transaction is targeted for a particular memory
bank on the calibration external bus.
The calibration chip selects are driven only by the EBI. External master accesses on the calibration bus are
not supported. In all other aspects, the calibration chip selects behave exactly as the primary chip selects.
See Section 12.4.1.5, “Memory Controller with Support for Various Memory Types” for details on chip
select operation.
12.2.1.17 Calibration Signals
The calibration signal functions are explained in Chapter 2, “Signal Description.”
DATA is not driven by the EBI during a calibration bus access. During a calibration bus access, the
non-calibration bus signals (other than DATA) are held in a negated state, with the exception of RD_WR
and ADDR, which reflect the same values shown on the calibration version of those signals. Because the
TS
and CS signals are held negated on the non-calibration bus during calibration accesses, no transfer
occurs on the EBI.
During an EBI bus access, the calibration bus signals (other than CAL_DATA) are held in a negated state.
CAL_DATA is not driven during non-calibration accesses.
Table 12-4. TSIZ[0:1] Encoding
Burst Cycle TSIZ[0:1] Transfer Size
N018-bit
N 10 16-bit
N 11 Invalid value
N 00 32-bit
Y00Burst