NXP Semiconductors MPC5566 - Delay Settings

Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-69
20.5.3 Delay Settings
Table 20-32 shows the values for the delay after transfer (t
DT
) and CS to SCK delay (t
CSC
) that can be
generated based on the prescaler values and the scaler values set in the DSPIx_CTARs. The values
calculated assume a 100 MHz system frequency.
20.5.4 MPC5xx QSPI Compatibility with the DSPI
Table 20-33 shows the translation of commands written to the TX FIFO command halfword with
commands written to the command RAM of the MPC5xx family QSPI. The table illustrates how to
configure the DSPIx_CTARs to match the default cases for the possible combinations of the MPC5xx
family control bits in its command RAM. The defaults for the MPC5xx family are based on a system clock
of 40 MHz.
Table 20-32. Delay Values
Delay Prescaler Values
(DSPI_CTAR[PBR])
1357
Delay Scaler Values (DSPI_CTAR[DT])
2
20.0 ns 60.0 ns 100.0 ns 140.0 ns
4
40.0 ns 120.0 ns 200.0 ns 280.0 ns
8
80.0 ns 240.0 ns 400.0 ns 560.0 ns
16
160.0 ns 480.0 ns 800.0 ns 1.1 μs
32
320.0 ns 960.0 ns 1.6 μs2.2 μs
64
640.0 ns 1.9 μs3.2 μs4.5 μs
128
1.3 μs3.8 μs6.4 μs9.0 μs
256
2.6 μs7.7 μs 12.8 μs 17.9 μs
512
5.1 μs 15.4 μs 25.6 μs 35.8 μs
1024
10.2 μs 30.7 μs 51.2 μs 71.7 μs
2048
20.5 μs 61.4 μs 102.4 μs 143.4 μs
4096
41.0 μs 122.9 μs 204.8 μs 286.7 μs
8192
81.9 μs 245.8 μs 409.6 μs 573.4 μs
16384
163.8 μs 491.5 μs 819.2 μ
s 1.1 ms
32768
327.7 μs 983.0 μs 1.6 ms 2.3 ms
65536
655.4 μs 2.0 ms 3.3 ms 4.6 ms