External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-17
The following table describes the fields in the EBI transfer error status register:
12.3.1.5 EBI Bus Monitor Control Register (EBI_BMCR)
The EBI_BMCR controls the timeout period of the bus monitor and whether it is enabled or disabled.
The following table describes the fields in the EBI bus monitor control register:
Table 12-8. EBI_TESR Field Descriptions
Field Description
0–29 Reserved.
30
TEAF
Transfer error acknowledge flag. Set if the cycle was terminated by an externally generated TEA signal.
0 No error
1 External TEA
occurred
This bit can be cleared by writing a 1 to it.
31
BMTF
Bus monitor timeout flag. Set if the cycle was terminated by a bus monitor timeout.
0 No error
1 Bus monitor timeout occurred
This bit can be cleared by writing a 1 to it.
Base + 0x000C Access: R/W
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BMT BME
0000000
W
Reset1111111110000000
Figure 12-4. EBI Bus Monitor Control Register (EBI_BMCR)
Table 12-9. EBI_BMCR Field Descriptions
Field Description
0–15 Reserved.
16–23
BMT[0:7]
Bus monitor timing. Defines the timeout period, in 8 external bus clock resolution, for the bus monitor. See
Section 12.4.1.7, “Bus Monitor,” for more details on bus monitor operation.
Timeout period
2 + (8 BMT)×
External bus clock frequency
----------------------------------------------------------------------------=
To Next Page
Loading...
