Boot Assist Module (BAM)
MPC5566 Microcontroller Reference Manual, Rev. 2
16-4 Freescale Semiconductor
• DISNEX bit in the SIU_CCR register to determine if the Nexus port is enabled
• MMU allows core access to MCU internal resources and the EBI
• EBI registers and external bus pads, when using external boot modes
• FlexCAN A, eSCI A and their pads, when using serial boot mode
• eDMA during serial boot mode
16.3.2 BAM Program Operation
The MCU core accesses the BAM after RSTOUT negates and before the application program executes.
The BAM program configures the e200z6 core MMU access for all MCU internal resources and external
memory, as shown in Table 16-2. The memory map configuration is the same for internal flash boot mode.
MMU maps the logical addresses to the same physical addresses for all modules except for the external
bus interface (EBI). The logical EBI addresses are mapped to physical addresses in internal flash memory.
This allows code developed to run from external memory to run from internal flash memory.
The BAM program reads the following data and determines the boot mode for the boot sequence:
• BOOTCFG[0:1] located in the reset status register (SIU_RSR)
• Censorship control field located at 0x00FF_FDE0 in the shadow row of internal flash
• Serial boot control field located at 0x00FF_FDE2 in the shadow row of internal flash
Table 16-2. MMU Configuration for Internal Flash Boot
TLB
Entry
Region Attributes
Logical Base
Address
Physical Base
Address
Size
0 Peripheral bridge B
and BAM
• Cache inhibited
• Guarded
• Big endian
• Global PID
0xFFF0_0000 0xFFF0_0000 1 MB
1 Internal flash • Cache enabled
• Not guarded
• Big endian
• Global PID
0x0000_0000 0x0000_0000 16 MB
2 EBI • Cache enabled
• Not guarded
• Big endian
• Global PID
0x2000_0000 0x0000_0000 16 MB
3 Internal SRAM • Cache inhibited
• Not guarded
• Big endian
• Global PID
0x4000_0000 0x4000_0000 256 KB
4 Peripheral bridge A • Cache inhibited
• Guarded
• Big endian
• Global PID
0xC3F0_0000 0xC3F0_0000 1 MB
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