NXP Semiconductors MPC5566 - RX 14 Mask (Canx_Rx14 Mask)

MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 22-17
22.3.3.4.2 RX 14 Mask (CANx_RX14MASK)
The CANx_RX14MASK register has the same structure as the RX global mask register and is used to
mask message buffer 14. Access to this register is unrestricted. Note that CANx_RX14MASK is
unaffected by soft reset (which occurs when CAN_MCR[SOFTRST] is asserted).
• Address offset: 0x0014
• Reset value: 0x1FFF_FFFF
22.3.3.4.3 RX 15 Mask (CANx_RX15MASK)
The CANx_RX15MASK register has the same structure as the RX global mask register and is used to
mask message buffer 15. Access to this register is unrestricted. Note that CANx_RX15MASK is
unaffected by soft reset (which occurs when CAN_MCR[SOFTRST] is asserted).
• Address offset: 0x0018
• Reset value: 0x1FFF_FFFF
22.3.3.5 RX Individual Mask Registers (CANx_RXIMR0 through CANx_RXIMR63)
By asserting the CANx_MCR[MBFEN] bit, the CANx_RXIMR[0–63] registers are used as acceptance
masks for received frame IDs, in both standard and extended ID formats. One mask register is provided
for each message buffer for individual ID masking per message buffer.
Address: Base + 0x0010 (CANx_RXGMASK)
Base + 0x0014 (CANx_RX14MASK)
Base + 0x0018 (CANx_RX15MASK)
Access: User read/write
0123456789101112131415
R 0 0 0
MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16
W
Reset
1
0001111111111111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0
W
Reset
1
1111111111111111
1
CANx_RXGMASK is unaffected by soft reset (which occurs when CAN_MCR[SOFTRST] is asserted).
Figure 22-6. RX Global Mask Register (CANx_RXGMASK)
Table 22-10. CANx_RXGMASK Field Descriptions
Field Description
0–2 Reserved, must be cleared.
3–13
MIn
Standard ID mask bits. These bits are the same mask bits for the standard and extended formats.
14–31
MIn
Extended ID mask bits. These bits are used to mask comparison only in extended format.