NXP Semiconductors MPC5566 - Timing and Connections for Asynchronous Memories

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-75
12.5.3.2 Timing and Connections for Asynchronous Memories
The connections to an asynchronous memory are the same as for a synchronous memory, except that the
CLKOUT, TS, and BDIP signals are not used. Figure 12-52 shows a block diagram of an MCU connected
to an asynchronous memory.
Figure 12-52. MCU Connected to Asynchronous Memory
Figure 12-53 shows a timing diagram of a read operation to a 16-bit asynchronous memory using three
wait states.
Figure 12-53. Read Operation to Asynchronous Memory, Three Initial Wait States
Flash memories typically use one WE signal as shown.*
MCU
Asynchronous
Memory
Note: On a 32-bit bus, RAM memories use all four WE/BE[0:3]. On a 16-bit bus, one
RAM memory uses WE/BE[0:1] and the other uses WE/BE[2:3].
ADDR[9:30]
A[0:21]
CAL_ADDR
DATA[0:15]
D[0:15]
CAL_DATA
WE/BE[0:3]
A[0:21]
CAL_WE
/BE[0:1]
OE
OE
CAL_OE
CS[0]
CE
CAL_CS[0]
CLKOUT
CS
n
OE
TS
ADDR[8:31]
DATA[0:31]
TA
WE[0:1]
3 wait states
DATA is valid