NXP Semiconductors MPC5566 - Pin Values after por Negates

Voltage Regulator Controller (VRC) and POR Module
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 23-7
23.5.3.3 Input Value of Pins During POR Dependent on V
DD33
To avoid selecting the bypass clock because PLLCFG[0:1] and RSTCFG were not treated as 1s when POR
negates, V
DD33
must not lag V
DDSYN
and the RESET pin power when powering the device by more than
the V
DD33_LAG
specification. V
DD33
can independently lag V
DDSYN
or RESET by more than the
V
DD33_LAG
specification. The V
DD33_LAG
specification applies regardless of whether V
RC33
is powered.
The V
DD33_LAG
specification only applies during power up. V
DD33
has no lead or lag requirements when
powering down.
Refer to the following sections or documents for more information:
Section 23.5.3.4, “Pin Values after POR Negates”
MPC5566 Microcontroller Data Sheet for the V
DD33_LAG
specification.
23.5.3.4 Pin Values after POR Negates
Depending on the final PLL mode required, the PLLCFG[0:1] and RSTCFG pins must have the values
shown in Table 23-2 after POR negates. Refer to application note AN2613, “MPC5554 Minimum Board
Configuration” for one example of the external configuration circuit.
NOTE
After POR negates, RSTCFG and PLLCFG[0:1] can change to their final
value, but do not switch through the 0, 0, 0 state on the pins.
Table 23-2. Values after POR Negation
Final PLL Mode RSTCFG PLLCFG[0] PLLCFG[1]
Crystal reference. Using RSTCFG
to select Crystal Reference as
the default.
1——
Crystal reference. Using RSTCFG to not select Crystal Reference
as the default.
—1—
External reference 0 1 1
Dual-controller — 1 —