Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-2 Freescale Semiconductor
19.1.1 Block Diagram
Figure 19-1 shows the primary components inside the eQADC.
Figure 19-1. Simplified eQADC Block Diagram
19.1.2 Overview
The eQADC transfers commands from multiple command FIFOs (CFIFOs) to the on-chip ADCs or to the
external device. The module can also in parallel (independently of the CFIFOs) receive data from the
on-chip ADCs or from an off-chip external device into multiple result FIFOs (RFIFOs). The eQADC
supports software and external hardware triggers from other modules to initiate transfers of commands
from the CFIFOs to the on-chip ADCs or to the external device. (Refer to Section 6.4.5.1, “eQADC
External Trigger Input Multiplexing.”) It also monitors the amount of memory currently in use by each the
CFIFO and RFIFO to detect underflow and overflow conditions.
Command
buffer 0
AN[8]_ANW
AN[9]_ANX
AN[10]_ANY
AN[11]_ANZ
AN[12:39]
REFBYPC
AN[7]_DAN3–
AN[6]_DAN3+
AN[5]_DAN2–
AN[4]_DAN2+
AN[3]_DAN1–
AN[2]_DAN1+
AN[1]_DAN0–
AN[0]_DAN0+
MUX
40:1
MA[0]
MA[1]
MA[2]
V
DDA
V
SSA
V
RH
V
RL
User-defined
command
queue
System
Memory
CFIFOn
ADC0
Result
format
and
calibration
submodule
Priority
ADC control
logic
FIFO control
unit
Decoder
BIAS
GEN
MUX
40:1
ADC1
Command
buffer 1
MUX
control
logic
User-defined
result
queue
eDMA and
Interrupt
requests
eDMA
transaction
done signals
eQADC SSI
transmit buffer
eQADC
Channel
number
(32-bits)
RFIFOn
(16-bits)
n = 0, 1, 2, 3, 4, 5
Signals at pins denoted by
NOTES:
eQADC
synchronous serial interface
(eQADC SSI)
FCK SDS SDO SDI
External Device
ETRIGn
REF
GEN
Pre-charge
are muxed on a single
package pin on some devices.
Command
buffer 2
Command
buffer 3
Refer to the Signals chapter
for a complete list of muxed
signals.
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