NXP Semiconductors MPC5566 - Etpu Channel Interrupt Enable Register (ETPU_CIER)

Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 18-37
18.4.5.5 eTPU Channel Interrupt Enable Register (ETPU_CIER)
The host interrupt enable bits for all 32 channels are grouped in ETPU_CIER. The bits are mirrored by the
channel configuration registers. For more information on channel configuration registers and interrupt
enable, refer to Section 18.4.6.2, “eTPU Channel n Configuration Register (ETPU_CnCR),” and the eTPU
Reference Manual.
Address: Base + 0x0000_0230 (eTPU A)
Address: Base + 0x0000_0234 (eTPU B)
Access: R/W1c
0123456789101112131415
RDTR
OS31
DTR
OS30
DTR
OS29
DTR
OS28
DTR
OS27
DTR
OS26
DTR
OS25
DTR
OS24
DTR
OS23
DTR
OS22
DTR
OS21
DTR
OS20
DTR
OS19
DTR
OS18
DTR
OS17
DTR
OS16
W
w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RDTR
OS15
DTR
OS14
DTR
OS13
DTR
OS12
DTR
OS11
DTR
OS10
DTR
OS9
DTR
OS8
DTR
OS7
DTR
OS6
DTR
OS5
DTR
OS4
DTR
OS3
DTR
OS2
DTR
OS1
DTR
OS0
W
w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-17. eTPU Channel Data Transfer Request Overflow Status Register (ETPU_CDTROSR)
Table 18-18. ETPU_CDTROSR Field Descriptions
Field Description
0–31
DTROSn
Channel n data transfer request overflow status.
0 indicates that no data transfer request overflow occurred in the channel
1 indicates that a data transfer request overflow occurred in the channel.
To clear a status bit, the host must write 1 to it.
For details about data transfer request overflow, refer to the eTPU Reference Manual.