MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 22-7
NOTE
Reading the control and status word (first word) of a message buffer locks
it from receiving further messages until it is unlocked by reading: another
message buffer, or the timer.
22.3.2 Message Buffer Structure
The message buffer structure used by the FlexCAN2 module is represented in Figure 22-2. Both extended
and standard frames (29-bit and 11-bit identifier, respectively) used in the CAN specification (version 2.0
Part B) are represented.
Table 22-3. Message Buffer MB0 Memory Mapping
Address
Offset
MB Field
0x80 Control and status (C/S)
0x84 Identifier field
0x88–0x8F Data fields 0–7 (1 byte each)
0 1 2 3 4 5 6 7 8 9 10 11 1213141516171819202122232425262728293031
0x0000
CODE
SRR
IDE
RTR
LENGTH TIME STAMP
0x0004
ID (Standard or Extended) ID (Extended)
0x0008 Data byte 0 Data byte 1 Data byte 2 Data byte 3
0x000C Data byte 4 Data byte 5 Data byte 6 Data byte 7
Figure 22-2. Message Buffer Structure
Table 22-4. Message Buffer Field Descriptions
Name Description
CODE Message buffer code. This 4-bit field can be accessed (read or write) by the CPU and by the
FlexCAN2 module itself, as part of the message buffer matching and arbitration process. The
encoding is shown in Table 2 2-5 and Tabl e 2 2 - 6. See Section 22.4, “Functional Description,” for
additional information.
SRR Substitute remote request. Fixed recessive bit, used only in extended format. It must be set to ‘1’
by the user for transmission (TX Buffers) and is stored with the value received on the CAN bus for
RX receiving buffers. It can be received as either recessive or dominant. If FlexCAN2 receives this
bit as dominant, then it is interpreted as arbitration loss.
0 Dominant is not a valid value for transmission in extended format frames
1 Recessive value is compulsory for transmission in extended format frames
IDE ID extended bit. This bit identifies whether the frame format is standard or extended.
0 Frame format is standard
1 Frame format is extended