NXP Semiconductors MPC5566 - Pad Configuration Registers 47 (SIU_PCR47)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-30 Freescale Semiconductor
Figure 6-23. DATA[18]_FEC_TX_ER_GPIO[46] Pad Configuration Registers (SIU_PCR46)
6.3.1.23 Pad Configuration Registers 47 (SIU_PCR47)
The SIU_PCR47 register controls the function, direction, and electrical attributes of
DATA[19]_FEC_RX_CLK_GPIO[47].
Figure 6-24. DATA[19]_FEC_RX_CLK_GPIO[47] Pad Configuration Registers (SIU_PCR47)
6.3.1.24 Pad Configuration Registers 48 (SIU_PCR48)
The SIU_PCR48 register controls the function, direction, and electrical attributes of
DATA[20]_FEC_TXD[0]_GPIO[48].
Figure 6-25. DATA[20]_FEC_TXD[0]_GPIO[48] Pad Configuration Registers (SIU_PCR48)
Address: Base + 0x009C Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as DATA[18] or FEC_TX_ER, the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When configured as DATA[18], FEC_TX_ER, or GPDO, set the IBE bit to 1 show the pin state in the GPDI register. Clear the
IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[18], clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[18] or FEC_TX_ER.
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
Address: Base + 0x009E Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as DATA[19] or FEC_RX_CLK, the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce
power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[19], clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[19] or FEC_RX_CLK.
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
Address: Base + 0x00A0 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as DATA[20] or FEC_TXD[0], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to
reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[20], set the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[20].
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1