MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor C-1
Appendix C
MPC5566 Reference Manual Revision History
This appendix describes corrections incorporated to the MPC5566 Microcontroller Reference Manual,
Rev. 1 to create revision 2. The corrections are listed chronologically, from changes to the first revision
published to the most recent changes located at the end of this appendix.
Each section details the changes between the last published revision and this published revision. Revision
changes are listed in sequential order by chapter, as shown in the following table:
C.1 Changes Between Revisions 1 and 2
Table C-1. MPC5566 Changes Between Revisions 1 and 2
Chapter Description
Chapter 1 Section 1.2, “Features”:
• Changed “Parallel programming mode to support rapid end of line programming” to “Page
programming mode to support rapid end of line programming”
• Added page footnote to read: Although this device has a maximum of 329 interrupts, the logic
requires that the total number of interrupts be divisible by four. Therefore, the total number of
interrupts specified for this device is 332.
Ta bl e 1 -3 MPC5500 Product Family Comparison:
• Changed to comply with the changes submitted for the marketing document.
Section 1.5, “MPC5500 Family Memory Map”:
• Added the following text about reserved bits and memory: Reserved register bits are allocated for
future products and have a default value of zero. When writing to a register, the reserved bits
default values must be written as well. Most device features are activated by writing a non-zero
value to them.
Reserved memory is allocated for future products, therefore do not write to memory segments
that are designated as reserved.
Section 1.2 Features: Under Operating Parameters: Changed to Fully static operation,
up to 144 MHz. Figure 1-1. Block Diagram: Changed 1 eQADC to 2 eQADC.
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