MPC5566 Reference Manual Revision History
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor C-2
Chapter 2
“Signal Description”
Ta bl e 2 -4 . Signal Description table: Changed footnote 3 to 1.3–3.3 V supplies are
±10%. Changed
footnote 16 to: The function of the MDO[11:4]_GPIO[82:75] pins is selected during a debug port
reset by the EVTI
pin or by selecting FPM in the NPC_PCR.
Added the following to Section 2.1, “Block DiagramRev. 2
To provide an extensive feature set as well as compatibility between the MPC5500 family of devices,
the majority of balls are assigned multiplexed signal functions.
Figure 2-1 shows only the signals that are available on the device. Signal functions that are not
available on this device are not shown in the diagram.
Ta bl e 2 -1 includes the primary signal functions that are not available on the device but are used as
pin labels in the Ball Grid Array (BGA) map. Read the last two columns in Ta bl e 2 - 1 for a comparison
of available signals on the package compared to the VertiCal assembly.
NOTE
The Vertical assembly has ball connections for all the available signals on the device.
Added to Ta ble 2 -1 MPC5566 Signal Properties, a footnote to PLLCFG[2]: “PLLCFG[2] must be tied
to ground.”
Added TXDA as an alternate signal to CNTXA_GPIO[83]; and RXDA as an alternate signal to
CNRXA_GPIO[84]. Added to graphic 2-2, table 2-3, and the signal description section.
Changed in Figure MPC5566 Signals: From: GPIO[4:27]_ADDR[6:7]_ADDR[8:31]
To: GPIO[4:25]_ADDR[8:29]
Added: GPIO[26:27]_ADDR[6:7]_ADDR[30:31]
Chapter 3
“e200z6 Core Complex”
Change to Table 3-11. Interrupts and Conditions, IVOR3:
• Access control.
• Precise external termination error and MSR[EE] = 1.
• Byte ordering due to:
• misaligned access across page boundary to pages with mismatched VLE bits
• access to pages with VLE set
with E indicating little-endian.
• Misaligned instruction fetch due to a change of flow to an odd halfword instruction boundary on
a Book E (non-VLE) instruction page as a result of the value in LR, CTR, or SRR0.
Additional description added to Table 3-11. Interrupts and Conditions for the following interrupts:
• Machine check
• Data Storage
• Instruction Storage
Chapter 4
“Reset”
Section “Watchdog Timer/Debug Reset” reworded.
Table C-1. MPC5566 Changes Between Revisions 1 and 2 (continued)
Chapter Description
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