NXP Semiconductors MPC5566 - Initialization;Application Information

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-75
17.5 Initialization/Application Information
Upon reset, all eMIOS unified channels default to general purpose inputs (GPIO input mode).
17.5.1 Considerations on Changing a UC Mode
Before changing an operating mode, program the UC to GPIO mode, and update EMIOS_CADRn and
EMIOS_CBDRn with the values for the next operating mode. The EMIOS_CCRn can be written with the
next operating mode. If a UC is changed from one mode to another without performing this procedure, the
first operating cycle of the selected time base is unpredictable.
NOTE
When interrupts are enabled and an interrupt is generated, clear the FLAG
bits before exiting the interrupt service routine.
17.5.2 Generating Correlated Output Signals
Correlated output signals can be generated by all output operating modes. Bits ODISn can be used to
control the update of these output signals.
To guarantee that the internal counters of correlated channels are incremented in the same clock cycle, the
internal prescalers must be set up before enabling the global prescaler. If the internal prescalers are set after
enabling the global prescaler, the internal counters can increment in the same ratio, but at a different clock
cycle.
Drive output disable input signals with the EMIOS_Flag_Out signals of some UCs running in SAIC mode.
When an output disable condition occurs, the software interrupt routine must service the output channels
before servicing the channels running SAIC. This procedure avoid glitches in the output pins.
17.5.3 Time Base Generation
For all channel operation modes that generate a time base (MC, OPWFM, OPWM, MCB, OPWFMB and
OPWMB), the internal counter rate can be modified by configuring the clock prescaler ratio. The clock
prescaler can use several ratios calculated as:
The prescaled clocks in Figure 17-58, Figure 17-59, and Figure 17-57 illustrate the time base generation
mechanism. Figure 17-60 shows the time base generation when using the internal clock set and clear on
match start.
Ratio GPRE 1+()UCPRE 1+()×=