NXP Semiconductors MPC5566 - Size, Alignment, and Packaging on Transfers

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-47
Figure 12-29. 32-Byte Read with Back-to-Back 16-Byte Bursts to 32-Bit Port, Zero Wait States
12.4.2.7 Size, Alignment, and Packaging on Transfers
Table 12-19 shows the allowed sizes that an internal or external master can request from the EBI. EBI
transfer request sizes not listed in the table are undefined. No error signal is asserted for these invalid cases.
Even though misaligned non-burst transfers from internal masters are supported, the EBI naturally aligns
the accesses when it sends them out to the external bus, splitting them into multiple aligned accesses if
necessary.
Natural alignment for the EBI means:
• Byte access can have any address
• 16-bit access, address bit 31 must equal zero
Table 12-19. Valid EBI Transaction Sizes (Number of Bytes)
Internal Master External Master
11
22
44
3
1
1
1
Some misaligned access cases can result in 3-byte writes. These
cases are treated as power-of-2 sized requests by the EBI, using
WE
/BE[0:3], to ensure only the correct 3 bytes are written.
8
32
Expects more data
CLKOUT
ADDR[8:31]
BDIP
DATA[0:31]
TA
RD_WR
TSIZ[0:1]
TS
OE
CS[n]
ADDR[29:31] = ‘000’
DATA is valid
00
ADDR[28:31] = ‘0000’
DATA is valid