External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-46 Freescale Semiconductor
Figure 12-28. 32-Byte Write Cycle with External TA, Basic Timing
12.4.2.6.3 Small Access Example #3: 32-byte Read to 32-bit Port with BL = 1
Figure 12-29 shows an example of a 32-byte read to a 32-bit burst enabled port with burst length of 4
words, requiring two 16-byte external transactions. For this case, the address for the second 4-word burst
access is calculated by adding 0x10 to the lower 5 bits of the first address (no carry), and then masking out
the lower 4 bits to fix them at zero.
Table 12-18. Examples of 4-word Burst Addresses
First Address
Lower 5 bits of the First
Address + 0x10 (no carry)
Final Second Address
(after masking lower 4 bits)
0x000 0x10 0x10
0x008 0x18 0x10
0x010 0x00 0x00
0x018 0x08 0x00
0x020 0x30 0x30
0x028 0x38 0x30
0x030 0x20 0x20
0x038 0x28 0x20
DATA is validDATA is valid
CLKOUT
ADDR[8:31]
TS
DATA[0:31]
TA
RD_WR
TSIZ[0:1]
BDIP
WE
CS[n]
AA + 4A + 8 A + 0xc
00
DATA is valid
This extra cycle is required after accesses 2, 4, and 6 to get the next 64-bits of internal write data.
*
Four more external accesses (not shown) are required to complete the internal 32-byte request.
The timing of these is the same as accesses 1-4 shown in this diagram.
**
12 34***
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