Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-5
20.1.4 Modes of Operation
The DSPI has four modes of operation. These modes can be divided into two categories; module-specific
modes such as master, slave, and module disable modes, and a second category that is an MCU-specific
mode: debug mode.
The module-specific modes are entered by host software writing to a register. The MCU-specific mode is
controlled by signals external to the DSPI. The MCU-specific mode is a mode that the entire device may
enter, in parallel to the DSPI being in one of its module-specific modes.
20.1.4.1 Master Mode
Master mode allows the DSPI to initiate and control serial communication. In this mode the SCK, PCSn
and SOUT signals are controlled by the DSPI and configured as outputs.
For more information, see Section 20.4.1.1, “Master Mode.”
20.1.4.2 Slave Mode
Slave mode allows the DSPI to communicate with SPI / DSI bus masters. In this mode the DSPI responds
to externally controlled serial transfers. The DSPI cannot initiate serial transfers in slave mode. In slave
mode, the SCK signal and the PCSx[0]_SS signal are configured as inputs and provided by a bus master.
PCSx[0]_SS must be configured as input and pulled high. If the internal pullup is being used then the
appropriate bits in the relevant SIU_PCR must be set (SIU_PCR [WPE = 1], [WPS = 1]).
For more information, see Section 20.4.1.2, “Slave Mode.”
20.1.4.3 Module Disable Mode
The module disable mode is used for MCU power management. The clock to the non-memory mapped
logic in the DSPI is stopped while in module disable mode. The DSPI enters the module disable mode
when the MDIS bit in DSPIx_MCR is set.
For more information, see Section 20.4.1.3, “Module Disable Mode.”
20.1.4.4 Debug Mode
Debug mode is used for system development and debugging. If the device enters debug mode while the
FRZ bit in the DSPIx_MCR is set, the DSPI halts operation on the next frame boundary. If the device enters
debug mode while the FRZ bit is cleared, the DSPI behavior is unaffected and remains dictated by the
module-specific mode and configuration of the DSPI.
For more information, see Section 20.4.1.4, “Debug Mode.”
To Next Page
Loading...
