NXP Semiconductors MPC5566 - Chapter 20; Peripheral Chip Select 4; Master Trigger (Pcsx[4]_Mtrig)

Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-7
20.2.2.3 Peripheral Chip Select 4 / Master Trigger (PCSx[4]_MTRIG)
PCSx[4] is a peripheral chip select output signal in master mode. In slave mode this signal is a master
trigger.
20.2.2.4 Peripheral Chip Select 5 / Peripheral Chip Select Strobe
(PCSx[5]_PCSS
)
PCSx[5] is a peripheral chip select output signal. When the DSPI is in master mode and the PCSSE bit in
the DSPIx_MCR is cleared to 0, the PCSx[5] signal selects the slave device that receives the current
transfer.
PCSS is a strobe signal used by external logic for deglitching of the PCS signals. When the DSPI is in
master mode and the PCSSE bit in the DSPIx_MCR is set to 1, the PCSS signal indicates the timing used
to decode PCSx[0:4] signals, which prevents glitches from occurring.
PCSx[5]_PCSS is not used in slave mode.
20.2.2.5 Serial Input (SINx)
SINx is a serial data input signal.
20.2.2.6 Serial Output (SOUTx)
SOUTx is a serial data output signal.
20.2.2.7 Serial Clock (SCKx)
SCKx is a serial communication clock signal. In master mode, the DSPI generates the SCK. In slave mode,
SCKx is an input from an external bus master.
20.3 Memory Map and Register Definition
20.3.1 Memory Map
Table 20-2 shows the DSPI memory map.
Table 20-2. DSPI Detailed Memory Map
Address Register Name Register Description Bits
Base:
0xFFF9_0000 (DSPI A)
0xFFF9_4000 (DSPI B)
0xFFF9_8000 (DSPI C)
0xFFF9_C000 (DSPI D)
DSPIx_MCR DSPI module configuration register 32
Base + 0x0004 — Reserved —
Base + 0x0008 DSPIx_TCR DSPI transfer count register 32
Base + 0x000C DSPIx_CTAR0 DSPI clock and transfer attributes register 0 32