NXP Semiconductors MPC5566 - Top Level Module Memory Map

Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
15-6 Freescale Semiconductor
15.3.1 Top Level Module Memory Map
The FEC implementation requires 1 KB of memory. This is divided into two sections of 512 bytes each:
• Section one contains the control and status registers
• Section two contains event and statistic counters held in the MIB block.
Table 15-1 defines the top level memory map. All accesses to and from the FEC memory map must be via
32-bit accesses. There is no support for accesses other than 32-bit.
15.3.2 Detailed Memory Map (Control and Status Registers)
Table 15-2 shows the FEC register memory map with each register address, name, and a brief description.
The base address of the FEC registers is 0xFFF4_C000.
NOTE
Some FEC memory locations and bits are not documented. The FEC
memory map is from 0xFFF4_C000–0xFFF4_C5FF. The memory and bits
are not required for the FEC software driver. They are used mainly by the
FEC subblocks for the FEC operation and are visible through the slave
interface.
Errant writes to these locations can corrupt FEC operation. Because the FEC
is a system bus master, errant writes can corrupt any part of the system
memory map. Errant writes to documented FEC memory locations can also
result is data corruption.
15.3.3 MIB Block Counters Memory Map
Table 15-2 defines the MIB Counters memory map which defines the locations in the MIB RAM space
where hardware-maintained counters reside. These fall in the 0xFFF4_C200–0xFFF4_C3FF address
offset range. The counters are divided into two groups.
• RMON counters are included which cover the Ethernet Statistics counters defined in RFC 1757. In
addition to the counters defined in the Ethernet Statistics group, a counter is included to count
truncated frames as the FEC only supports frame lengths up to 2047 bytes. The RMON counters
are implemented independently for transmit and receive to insure accurate network statistics when
operating in full duplex mode.
•IEEE® counters are included which support the Mandatory and Recommended counter packages
defined in section 5 of ANSI/IEEE® Std. 802.3 (1998 edition). The IEEE® Basic Package objects
are supported by the FEC but do not require counters in the MIB block. In addition, some of the
Table 15-1. FEC Module Memory Map
Address Function
Base address FFF4_C000–FFF4_C1FF Control and status registers
FFF4_C200–FFF4_C3FF MIB block counters